Modern system on chips (SoCs) and other integrated circuits (ICs) are designed with low power directives to achieve longer battery life. Debug of such ICs and SoCs is extremely challenging due to multiple low power domains that are designed in the devices that wake up and sleep with much higher granularity compared to previous generations. Currently available debug solutions provide limited capability to perform debugging of firmware and low power operation.
Another debug concern is that debug bandwidth may be insufficient, especially if debug data from concurrent use cases and features are sent in-band with functional traffic, which can lead to a bottleneck that is typically resolved in favor of the functional traffic. In some cases, it is also possible that debug traffic colliding with functional traffic changes a debug scenario, and as a result debugging becomes difficult.